Simulation Framework for Analyzing Reconfigurable Architectures
Hardware Reconfiguration of Microelectronic Components in Self-Optimizing Mechatronic Systems.
In subproject C1 we develop methods for the efficient use of dynamically reconfigurable hardware in self-optimizing mechatronic systems. On one hand it should be possible to use these approaches efficiently in existing systems. On the other hand, they should lead to scalable system concepts that can be implemented efficiently in future microelectronic technologies. Therefore, we are developing, modelling, and evaluating new architectural concepts for reconfigurable systems with a focus on resource efficiency.
Methods for partial reconfi- guration
If the principles of self-optimization are extended to the topology and structure of the microelectronic systems that are used, we need system architectures and individual system components to be reconfigurable. In this subproject we therefore plan to develop a methodology for the efficient use of dynamically reconfigurable hardware in self-optimizing mechatronic systems. During the first two funding phases we analyzed the cost-benefit ratio of dynamically reconfigurable hardware. Based on the models created in this course of work, we then developed new methods for dynamically positioning hardware modules and optimizing information technology components in a running system. As a practical implementation we have created a reconfigurable system environment based on state-of-the-art field-programmable gate arrays (FPGAs), which makes optimal use of the currently available technologies.
In this project a design framework for the development and analysis of self-optimizing hardware systems has been established, that is widely used in the CRC614. The DMC model and the simulation environment SARA provide the user with a complete simulation flow that enables the analysis of dynamically reconfigurable systems on a high level of abstraction. This has been utilized to develop and evaluate new methods for placement and defragmentation of hardware modules. As an example, first results concerning defragmentation for heterogeneous systems have been presented.
The new methodologies are verified for various application scenarios in close cooperation with the other subprojects. In the course of the CRC614 it is of vital importance to enable switching between the miscellaneous configurations in real-time. For the realization of the proposed concepts we use our dynamically reconfigurable prototyping system RAPTOR-X64 as well as a newly developed mini robot platform, which is especially suitable for the realization of distributed reconfigurable systems. The information processing of both systems is widely compatible, so that the concepts for dynamic reconfiguration that are developed in the CRC614 can be utilized on both platforms.
Currently, the scope of our work is extended to distributed self-optimizing systems. Our goal is the realization of a robust information processing platform based on distributed dynamically reconfigurable components. An important challenge is, in addition to an increase in reliability, the optimization of the resource efficiency, i.e., the optimization of performance, cost and energy consumption. If subcomponents fail, the overall system should be able to adapt in a self-optimizing manner to the new conditions. This can be realized, e.g., by reconfiguring several subcomponents or the communication infrastructure at runtime
RAPTOR-X64 Rapid-Prototyping- System
In addition to dynamically reconfigurable systems based on fine-grained FPGAs we have accomplished first analyses in respect to coarse-grained, processor-based architectures. Our approach is based on on-chip parallel processors that can be adapted to varying operational conditions by reconfiguration at runtime. Our goal is to maximize the positive effects of reconfiguration while minimizing the additional cost. The new, dynamically reconfigurable multiprocessor architectures will be prototypically implemented and evaluated with respect to their resource efficiency.
Coordinator of the Subproject:
Publications (since 6/2005)
Reviewed Publications
Chinapirom, T.; Witkowski, U.; Rückert, U.: Dynamic Reconfiguration of Universal FPGA-Microcontroller Module. In: FIRA RoboWorld Congress, December 10-14, 2005, Singapore City, Singapore, Elsevier, 2005
El-habbal, M.; Witkowski, U.; Rückert, U.: FPGA based speech processing for the Khepera Robot. In: In Proceedings of the 4th International Symposium on Autonomous Minirobots for Research and Edutainment (AMiRE), October 2-5, 2007, Buenos Aires, Argentine, Springer-Verlag, 2007
Griese, B.; Kettelhoit, B.; Porrmann, M.: Evaluation of on-chip interfaces for dynamically reconfigurable coprocessors. In: Proceedings of the 5th International Symposium on Parallel Computing in Electrical Engineering (PARELEC), September 13-17, 2006, Bialystok, Poland, IEEE Computer Society Press, 2006, pp. 214-219
Griese, B.; Oberthür, S.; Porrmann, M.: Component case study of a self-optimizing RCOS/RTOS system: A reconfigurable network service. In: Rettberg, A., Zanella, M. C., Rammig, F. J. E.: From Specification to Embedded Systems Application, International Embedded Systems Symposium (IESS), August 15-17, 2005, Manaos, Brazil, Springer, 2005, pp. 267-277
Griese, B.; Porrmann, M.: A Reconfigurable Ethernet Switch for Self-Optimizing Communication Systems. In: Proceedings of the 3rd Conference on Computing Frontiers, May 3-5, 2006, Ischia, Italy, ACM, New York, NY, USA, 2006, pp. 403-412
Grünewald, M.; Rust, C.; Witkowski, U.: Using mini robots for prototyping intersection management of vehicles. In: Proceedings of the 3rd International Symposium on Autonomous Minirobots for Research and Edutainment, September 20-22, Awara-Spa, Fukui, Japan, Springer-Verlag New York, Inc., Secaucus, NJ, USA, 2005, pp. 287-292
Hagemeyer, J.; Kettelhoit, B.; Koester, M.; Porrmann, M.: A Design Methodology for Communication Infrastructures on Partially Reconfigurable FPGAS. In: Proceedings of the 17th International Conference on Field Programmable Logic and Applications (FPL), AUGUST 27-29, 2007, Amsterdam, Netherlands, IEEE, 2007, pp. 331-338
Hagemeyer, J.; Kettelhoit, B.; Koester, M.; Porrmann, M.: Design of Homogeneous Communication Infrastructures for Partially Reconfigurable FPGAs. In: Proc. of the Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), June 25 - 28, 2007, Las Vegas, Nevada, USA, CSREA Press, 2007
Hagemeyer, J.; Kettelhoit, B.; Koester, M.; Porrmann, M.: INDRA-Integrated Design Flow for Reconfigurable Architectures. In: Proceedings of the International Conference on Design, Automation and Test in Europe (DATE), April 16-20, 2007, Nice, France, IEEE Computer Society Press, 2007
Hagemeyer, J.; Kettelhoit, B.; Porrmann, M.: Dedicated Module Access in Dynamically Reconfigurable Systems. In: Proceedings of the 20th IEEE International Parallel and Distributed Processing Symposium, April 25-29, Rhodes Island, Greece, IEEE, 2006
Hagemeyer, J.; Koester, M.; Porrmann, M.: Hardware Virtualization Exploiting Dynamically Reconfigurable Architectures. In: Brinkmann, A., Karl, H. (Eds.): 1. GI/ITG KuVS Fachgespräch Virtualisierung, February 11-12, 2008, Paderborn, Germany, Universität Paderborn, 2008, pp. 19-28
Hussmann, M.; Thies, M.; Kastens, U.; Purnaprajna, M.; Porrmann, M.; Rückert, U.: Compiler-Driven Reconfiguration of Multiprocessors. In: Proceedings of Workshop on Application Specific Processors (WASP), October 4-5, 2007, Salzburg, Austria, 2007, pp. 3-10
Kaulmann, T.; Chinapirom, T.; Witkowski, U.; Rückert, U.: Universal mini-robot with micro-processor and reconfigurable hardware. In: Proceedings of FIRA RoboWorld Congress, June 30 - July 1, 2006, Dortmund, Germany, Springer-Verlag, 2006, pp. 137-142
Kaiser, I.; Kaulmann, T.; Gausemeier, J.; Witkowski, U.: Miniaturization of autonomous robots by the new technology Molded Interconnected Devices (MID). In: Proceedings of the 4th International Symposium on Autonomous Minirobots for Research and Edutainment (AMiRE), October 2-5, Buenos Aires, Springer-Verlag, 2007, pp. 107-114
Koester, M.; Kalte, H.; Porrmann, M.: Run-Time Defragmentation for Partially Reconfigurable Systems. In: Proceedings of the International Conference on Very Large Scale Integration of System-on-Chip (IFIP VLSI-SoC), October 17-19, 2005, Perth, Australia, 2005, pp. 109-115
Koester, M.; Kalte, H.; Porrmann, M.: Task Placement for Heterogeneous Reconfigurable Architectures. In: Proceedings of the IEEE 2005 Conference on Field-Programmable Technology (FPT), December 11-14, 2005, Singapore City , Singapore, 2005, pp. 43-50
Koester, M.; Kalte, H.; Porrmann, M.: Relocation and Defragmentation for Heterogeneous Reconfigurable Systems. In: Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), June 27-30, 2006, Las Vegas, USA, CSREA Press, 2006, pp. 70-76
Koester, M.; Kalte, H.; Porrmann, M.; Rückert, U.: Defragmentation Algorithms for Partially Reconfigurable Hardware. VLSI-SoC: From Systems to Silicon. IFIP International Federation for Information Processing Series, 240, Springer, Boston, USA, 2007, pp. 41-53
Koester, M.: Efficient Utilization of Partially Reconfigurable Hardware. In: Proceedings of the International Conference on Very Large Scale Integration of System-on-Chip (IFIP VLSI-SoC), October 17-19, 2005, Perth, Australia, 2005, pp. 597-598
Kalte, H.; Porrmann, M.: Context Saving and Restoring for Multitasking in Reconfigurable Systems. In: 15th International Conference on Field Programmable Logic and Applications (FPL), August 24-28, 2005, Tampere, Finland, IEEE, 2005, pp. 223-228
Kalte, H.; Porrmann, M.: REPLICA2Pro: Task Relocation by Bitstream Manipulation in VIRTEX-II/Pro FPGAs. In: CF '06: Proceedings of the 3rd conference on Computing frontiers, 2006, Ischia, Italy, ACM, New York, NY, USA, 2006, pp. 403-412
Kettelhoit, B.; Porrmann, M.: A Layer Model for Systematically Designing Dynamically Reconfigurable Systems. In: Proceedings of the 16th International Conference on Field Programmable Logic and Applications (FPL), August 28-30, 2006, Madrid, Spain, IEEE, 2006, pp. 547-552
Kaulmann, T.; Strünkmann, M.; Witkowski, U.: FPGA-based Object Detection in Robot Soccer Application. In: Proceedings of the 3rd International Symposium on Autonomous Minirobots for Research and Edutainment (AMiRE), September 20-22, Awara-Spa, Fukui, Japan, Springer-Verlag, 2005, pp. 135-140
Münch, E.; Gambuzza, A.; Paiz, C.; Pohl, C.; Porrmann, M.: FPGA-in-the-Loop Simulations with CAMEL-View. In: In Proceedings of the 7th International Heinz Nixdorf Symposium, February 20-21, 2008, Paderborn, Germany, HNI-Verlagsschriftenreihe, 2008, pp. 429-445
Niemann, J.-c.; Puttmann, C.; Porrmann, M.; Rückert, U.: Resource Efficiency of the GigaNetIC Chip Multiprocessor Architecture. Journal of Systems Architecture (JSA), special issue on Architectural premises for pervasive computing, 53, 2007, pp. 285-299
Paiz, C.; Chinapirom, T.; Witkowski, U.; Porrmann, M.: Dynamically Reconfigurable Hardware for Autonomous Mini-Robots. In: 32nd Annual Conference of the IEEE Industrial Electronics Society (IECON), November 7-10, 2006, Paris, France, IEEE Industrial Electronics Society, 2006, pp. 3981-3986
Paiz, C.; Kettelhoit, B.; Klassen, A.; Porrmann, M.; Rückert, U.: Dynamically Reconfigurable Hardware for Digital Controllers in Mechatronic Systems. In: IEEE International Conference on Mechatronics (ICM), July 10-12, 2005, Taipei, Taiwan, IEEE, 2005, pp. 675-680
Paiz, C.; Kettelhoit, B.; Porrmann, M.: A design framework for FPGA-based dynamically reconfigurable digital controllers. In: The IEEE International Symposium on Circuits and Systems (ISCAS), May 27-30, 2007, New Orleans, USA, IEEE, 2007, pp. 3708-3711
Porrmann, M.; Niemann, J.-c.: Teaching Reconfigurable Computing - Theory and Practice. In: International Workshop on Reconfigurable Computing Education, March 1, 2006, Karlsruhe, Germany, 2006
Paiz, C.; Porrmann, M.: The Utilization of Reconfigurable Hardware to Implement Digital Controllers: a Review. In: IEEE International Simposium on Industrial Electronics (ISIE), June 4-7, 2007, Vigo, Spain, IEEE Industrial Electronics Society, 2007, pp. 2380-2385
Purnaprajna, M.; Porrmann, M.: Run-time Reconfigurable Cluster of Processors. In: 41st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-41 2008), Workshop on Design, Architecture and Simulation of Chip Multi-Processors, November 8-12, 2008, Lake Como, Italy, IEEE Computer Society, 2008
Purnaprajna, M.; Porrmann, M.: Run-time Reconfigurable Multiprocessors. In: 23rd IEEE International Parallel and Distributed Processing Symposium, PhD Forum, March, 2008, Miami, FL, USA, 2008
Paiz, C.; Pohl, C.; Porrmann, M.: Reconfigurable Hardware in-the-Loop Simulations for Digital Control Design. In: 3rd International Conference on Informatics in Control, Automation and Robotics (ICINCO), May 9-12, 2006, Setubal, Portugal, 2006, pp. 39-46
Pohl, C.; Paiz, C.; Porrmann, M.: Hardware-in-the-Loop Entwicklungsumgebung für informationsverarbeitende Komponenten mechatronischer Systeme. 5. Paderborner Workshop Entwurf mechatronischer Systeme, March 22-23, 2007, Paderborn, Germany, Heinz Nixdorf Institut, Universität Paderborn, 2007, pp. 69-79
Paiz, C.; Pohl, C.; Porrmann, M.: Hardware-in-the-Loop Simulations for FPGA-Based Digital Control Design. Informatics in Control, Automation and Robotics, Volume 3, Springer-Verlag, 2008, pp. 355-372
Pohl, C.; Paiz, C.; Porrmann, M.: A Hardware-in-the-Loop Design Environment for FPGAs. In: Design, Automation and Test in Europe DATE, University Booth, March 10-14, 2008, Munich, Germany, 2008
Pohl, C.; Paiz, C.; Porrmann, M.: vMAGIC - VHDL Manipulation and Automation for Reliable System Development. In: Proceedings of the 3rd International Workshop on Reconfigurable Computing Education, April 10, 2008, Montpellier, France, 2008
Purnaprajna, M.; Puttmann, C.; Porrmann, M.: Power Aware Reconfigurable Multiprocessor for Ellipic Curve Cryptography. In: Proceedings of the Conference on Desing, Automation and Test in Europe (DATE), March 10-14, 2008, Munich, Germany, 2008, pp. 1462-1467
Rana, V.; Santambrogio, M.; Sciuto, D.; Kettelhoit, B.; Koester, M.; Porrmann, M.; Rückert, U.: Partial Dynamic Reconfiguration in a Multi-FPGA Clustered Architecture Based on Linux. In: Proceedings of the 21th International Parallel and Distributed Processing Symposium (IPDPS) / Reconfigurable Architectures Workshop (RAW), March 26- 27, 2007, Long Beach, California, USA, 2007
Schulz, B.; Paiz, C.; Hagemeyer, J.; Mathapati, S.; Porrmann, M.; Boecker, J.: Run-Time Reconfiguration of FPGA-Based Drive Controllers. In: 12th European Conference on Power Electronics and Applications (EPE), September 2-5, 2007, Aalborg, Denmark, 2007
Tanoto, A.; Du, J. L.; Kaulmann, T.; Witkowski, U.: MPEG-4-Based Interactive Visualization as an Analysis Tool for Experiments in Robotics. In: MSV'06 - The 2006 International Conference on Modeling, Simulation and Visualization Methods, June 26-29, 2006, Las Vegas, Nevada, USA, 2006
Tanoto, A.; Du, J. L.; Witkowski, U.; Rückert, U.: Teleworkbench: An Analysis Tool for Multi-Robotic Experiments. In: Proceedings of IFIP BICC, August 20-25, 2006 Santiago de Chile, Chile, 2006, pp. 179-188
Twiefel, J.; Klubal, M.; Paiz, C.; Mojrzisch, S.; Krüger, H.: Digital signal processing for an adaptive phase-locked loop controller. In: SPIE Smart Structures and Materials & Nondestructive Evaluation and Health Monitoring, January, 2008, San Diego, California USA, SPIE-The International Society for Optical Engineering, 2008
Tanoto, A.; Witkowski, U.; Rückert, U.: Teleworkbench: A Teleoperated Platform for Multi-Robot Experiments. In: Proceedings of the 3rd International Symposium on Autonomous Minirobots for Research and Edutainment (AMiRE), September 20-22, 2005, Awara-Spa, Fukui, Japan, 2005, pp. 49-54
Witkowski, U.; Herbrechtsmeier, S.; El-habbal, M.; Rückert, U.: Powerful Miniature Robot For Research And Education. In: The 5th International Conference on Computational Intelligence, Robotics and Autonomous System (CIRAS), June 19 - 21, 2008, Linz, Austria, 2008
Witkowski, U.; Herbrechtsmeier, S.; Tanoto, A.; El-habbal, M.; Alboul, L., P. J.: Self-Optimizing Human-Robot Systems for Search and Rescue in Disaster Scenarios. The 7th International Heinz Nixdorf Symposium, February 20-21, 2008, Paderborn, Germany, 2008, pp. 315-329
Ph.D.-Theses
Griese, B.: Adaptive Echtzeitkommunikationsnetze. Dissertation, Fakultät für Elektrotechnik, Informatik und Mathematik, Universität Paderborn, HNI-Verlagsschriftenreihe, Paderborn, 2008
Kettelhoit, B.: Architektur und Entwurf dynamisch rekonfigurierbarer FPGA-Systeme. Dissertation, Fakultät für Elektrotechnik, Informatik und Mathematik, Universität Paderborn, HNI-Verlagsschriftenreihe, Paderborn, 2008
Köster, M.: Analyse und Entwurf von Methoden zur Ressourcenverwaltung partiell rekonfigurierbarer Architekturen. Dissertation, Fakultät für Elektrotechnik, Informatik und Mathematik, Universität Paderborn, HNI-Verlagsschriftenreihe, Paderborn, Band 14-231, 2007
Niemann, J.-c.: Ressourceneffiziente Schaltungstechnik eingebetteter Parallelrechner - GigaNetIC. Dissertation, Fakultät für Elektrotechnik, Informatik und Mathematik, Universität Paderborn, HNI-Verlagsschriftenreihe, Paderborn, 2008
